1. Field of the Invention
The present invention relates to lead end grid array semiconductor packages, and, more particularly to a lead end grid array semiconductor package having a leadframe with a plurality of leads wherein each lead is provided with a protrusion on the lower surface and outer end of each lead.
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the leadframe are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are then used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook, (1989), edited by R. Tummala and E. Rymaszewski, incorporated by reference herein. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1xc3x971 mm to 10xc3x9710 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.
The requirement for such semiconductor packages has resulted in developments of semiconductor packages having a structure in which leads are exposed on the bottom of an encapsulate at respective lower surfaces thereof. Such a semiconductor package is called a xe2x80x9clead end grid array semiconductor package. Currently, the demand for semiconductor packages having such a structure is increasing.
However, a typical lead end grid array semiconductor package has a partially etched structure at the lower surfaces of the outer lead ends that may result in a separation of bonding wires during a wire bonding process involved in the fabrication of the semiconductor package. Additionally, during the molding process a less than ideal clamping may occur during the fabrication of the semiconductor package. The deficiency in clamping may be due to variations in flatness at a lower surface because the lower surfaces of the outer ends of the leads are partially etched. Due to these variations in flatness, the leads may have a non-uniform flatness during a wire bonding process that is conducted at a high temperature and a high pressure even though the lower surfaces of the outer lead ends are supported by a heat block adapted to support a leadframe carrying those leads. For this reason, bonding wires may be insecurely bonded or rise at their ends. As a result, a separation of those bonding wires may occur. In the molding process conducted at a high temperature and a high pressure, a degraded clamping may also occur due to the non-uniform flatness of the leads caused by the etching process. Poor clamping may result in lands on the ends of protrusions that extend from the lower surface of the leads which may become buried in the resin encapsulate. Another undesirable result is that the molding resin may leak from the encapsulating region. As a result, a degraded package maybe produced.
The present invention relates to a lead end grid array semiconductor package of improved design and reliability. More particularly, the present invention relates to a lead end grid array semiconductor package that comprises a leadframe having a chip paddle and a semiconductor chip located on the chip paddle. A plurality of leads are present on the leadframe body. Conductive wires are provided for electrically connecting the leads to bond pads on the semiconductor chip. The leads extend outwardly from the chip paddle, and each of the leads has an outer end that defines an outer perimeter of the leadframe. A plurality of inner protrusions and outer protrusions are located on a lower surface of the leads. The outer protrusions communicate with the outer perimeter of the leadframe. An encapsulate encapsulates the semiconductor chip and the conductive wires to form the semiconductor package. Solder balls are attached to a lower surface of the protrusions. To form the semiconductor package, a plurality of leads are formed on the leadframe and a plurality of protrusions are formed on a lower surface of the leads, wherein at least one of the protrusions is in communication with a perimeter of the leadframe. To affix the conductive wires to bond pads, the leadframe is positioned on a flat heat block. A ball of conductive material is affixed to the lower end of the protrusions to form the ball grid array.
In another aspect, the above described present invention includes encapsulating the semiconductor chip, wires and leads in an encapsulating material. The leads may be arranged along the edges of the chip paddle.